The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure within any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs.
Increasingly dense circuit design has not only improved a number of performance characteristics, it has also created a number of critical circuit design challenges. One such challenge concerns device-to-device component variations. Many applications, particularly mixed-signal applications (e.g., a target frequency oscillation), require fixed-value components. Slight changes in the effective capacitance, resistance or inductance of a semiconductor circuit can, depending upon the application, substantially alter the performance of a system—rendering it unreliable or inoperable.
Unfortunately, certain fundamental integrated circuit (IC) components (e.g., resistors, capacitors, inductors, transistors) are highly susceptible to variance (e.g., device-to-device, lot-to-lot). Minor variations in semiconductor fabrication processes can result in substantial performance disparities between identical devices. For example, in typical CMOS technologies, component variations generally range between about ±10% and about ±30%. Where a parameter of interest is the product of two or more component values (e.g., RC, LC, etc.), the single component variations can combine to have a substantial cumulative effect (e.g., ±50% or more).
In an effort to address component variations, semiconductor manufacturers have employed certain methods to calibrate component values—to provide some semblance of device-to-device consistency. This calibration is typically achieved either by trimming the component, during the test phase of production, using laser technology, or by modifying the component's effective value through use of a programmable binary-weighted array. Generally, component arrays are “programmed” by blowing fuses to select desired array is elements. The array is designed to have a nominal center value equal to the desired component value, with an array range larger than the possible spread of process variations. Usually, the array is programmed (i.e., blown fuses are selected) by way of a digital input code to a digital to analog converter (DAC). Both such methods are expensive, due either to the extra steps introduced during processing to implement the fuses or the test time needed for the laser-trimming procedure. Furthermore, both such methods are irreversible—which can present problems over time. The value of a calibrated device can change over time, due to the device's aging or the influence of other non-process related factors (e.g., temperature, stress).
Some attempts have been made to provide re-programmable arrays using linear DACs. Unfortunately, designers utilizing such systems have typically been faced with a making a trade-off between the size of the DAC and the ultimate accuracy of the component calibration value. A DAC with an infinite number of bits could, theoretically, provide an infinitely small step size between bits—allowing for a very precise, if not exact, component calibration. Practically, however, most device layouts are simply not capable of accommodating large DACs—especially not infinitely large DACs. Generally speaking, DACs on the order of 12 to 15 bits are typically too cumbersome to implement in most high-density IC devices. Frequently, size and layout limitations permit DACs on the order of 10 or fewer bits.
With DACs of this size, the step size between bits is not trivial. Often, a desired component calibration value falls in between bits. Further complicating matters, process anomalies during device fabrication typically introduce a number of variances into the bit-to-bit step sizes. For example, in a 3-bit DAC, the step between 010 and 011 may be, for example, 15% smaller than the step between 011 and 100, which itself may be, for example, 12% larger than the step between 100 and 101. Thus, where a desired component calibration value falls somewhere within a larger bit-to-bit step, highly precise (i.e., <1.0%) calibration may not be possible. Commonly, however, mixed signal device applications can require calibration of 0.5% or better.
Unable to construct a DAC of infinitely large bit size, conventional systems have focused on improving the linearity of a DAC (i.e., minimizing the variance in bit-to-bit step sizes). Such conventional systems have often focused on improving the uniformity of element sizes, and optimizing the layout and placement of elements, in order to produce a greater degree of linearity in the DAC. Unfortunately, however, such efforts are rarely able to completely mitigate the anomalies and variances introduced by fabrication processes, and frequently these efforts add considerable overhead and cost to design and layout processes.
As a result, there is a need for a high-resolution device calibration system that readily provides precise calibration in high-density IC designs in an easy, efficient and cost-effective manner.